In spite of improvement of high integration of semiconductor integrated circuits and miniaturization of semiconductor chips, it has been difficult to reduce the size of a pad having a region electrically connected with the external components to a satisfactory level. This is because a pad has to be provided with a certain dimension to ensure stable electric connection with bonding wires, bumps, and the like, and to avoid a high resistance in the connecting point.
In addition, for a pad on which a bump is formed, it should be considered to keep adequate coverage for an aperture in a protective insulating layer. If there is a large and steep step around an aperture in a protective insulating layer, a barrier layer may not exhibit adequate coverage, resulting in breakage of the barrier layer.
For example, Japanese Patent Application Laid-open No. 10-189606 discloses a technique to attempt to overcome such a problem. In the technique of this patent application, a protective insulating layer formed on a metal pad of a semiconductor substrate has a connection aperture having steps for a bump of a semiconductor device. In forming such a protective insulating layer, an insulating layer on a metal pad is subjected to photo etching several times using a plurality of masks with different diameters to form an aperture having steps. Since this method requires a number of photolithography steps, a plurality of photo-masks are necessary for the photolithographic operation. As a result, although the coverage of the barrier layer is improved by this method, a cleaning step or the like is required during and prior to each photolithographic operation. This results in an undesirable increase in the number of fabrication steps and production costs.